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AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
t ( SMPS ? START ) =
Power-Up Sequence (POR, UVLO, PGD_IN)
Power-on reset (POR) occurs when V CC rises above
approximately 2V, resetting the fault latch and prepar-
ing the controller for operation. The V CC undervoltage
lockout (UVLO) circuitry inhibits switching until V CC
rises above 4.25V. The controller powers up the refer-
ence once the system enables the controller —V CC
above 4.25V and SHDN driven high. With the reference
in regulation, the controller ramps the SMPS and
NBV_BUF voltages to the boot voltage set by the SVC
and SVD inputs:
V BOOT
( 1 mV / μ s )
after the SMPS outputs reach regulation. The boot VID is
stored the first time PWRGD goes high. The MAX17009
is in pulse-skipping mode during soft-start, and in
forced-PWM mode soft-shutdown.
The NB regulator soft-start time is set by the NB regula-
tor soft-start timer, or by t (NBV_BUF-START) , whichever is
longer.
For automatic startup, the battery voltage should be
present before V CC . If the controller attempts to bring
the output into regulation without the battery voltage
present, the fault latch trips. The controller remains shut
down until the fault latch is cleared by toggling SHDN
or cycling the V CC power supply below 0.5V.
t ( NBV _ BUF ? START ) =
V BOOT R TIME C NBV _ BUF
( 7 μ A × 143 k Ω )
If the V CC voltage drops below 4.25V, the controller
assumes that there is not enough supply voltage to
make valid decisions and could also result in the stored
The soft-start circuitry does not use a variable current
limit, so full output current is available immediately.
PWRGD becomes high impedance approximately 20μs
boot VIDs being corrupted. As such, the MAX17009
immediately stops switching (DH_ and DL_ pulled low),
latches off, and discharges the outputs using the inter-
nal 10 Ω switches from CSL_ to GND. See Figure 6.
1
2
3
4
5
6
DC_IN
V DDIO
SVC/SVD
2-BIT BOOT VID
SERIAL MODE
BUS IDLE
SHDN
GNDS2
(VDD_PLANE_STRAP)
7
V CORE_
V NBV_BUF
20 μ s
BLANK
PWRGD
10 μ s
HIGH IMPEDANCE
20 μ s
PGD_IN
RESET_L
8
Figure 6. Startup Sequence
30
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